1. Field of the Invention
The invention relates to semiconductor processing, and in particular, a dual gate oxide process for high performance DRAM systems or logic circuits, in which the oxide thicknesses are of greater uniformity.
2. Description of the Related Art
In high performance DRAM systems or logic circuits, it is necessary to integrate Dual Gate Oxide (DGO) thicknesses into a single integrated circuit device.
One reason for performing dual gate oxide processing is due to the fact that high performance transistors require thinner gate dielectric regions and operate at lower voltages from about 1.4 to 2.5 volts, whereas most common external peripherals require higher operating voltages of from about 3.3 to 5.0 volts.
One typical way to achieve two oxide thicknesses in one oxidation step is to make use of local nitrogen implantation to reduce the oxidation rate at the implanted sites.
The use of local nitrogen implementation to achieve two oxidation thicknesses in one oxidation step consist of utilizing the process integration scheme of:
growing of the sacrificial oxide; PA1 implantation of dopants through the sacrificial oxide; PA1 employing a photoresist mask to pattern an integrated circuit that includes the first transistor having a first dielectric thickness and a second transistor having a second dielectric thickness; PA1 implanting nitrogen ions to create dual gate oxide devices; PA1 stripping off the photoresist mask and the sacrificial oxide; and PA1 subjecting the gate to oxidation. PA1 forming a first oxide layer over both the first and second active areas; PA1 forming a protection layer over the first oxide layer; PA1 masking the protection layer overlying the first active area; PA1 etching the protection layer and the first oxide layer overlying the second active area while the masking layer protects the first oxide layer and the protection layer overlying the first active area; PA1 forming a second oxide layer overlying the second active area where the protection layer prevents oxidation in the first active area; and PA1 forming conductive gate electrodes over the first and second active areas wherein a composite of the protection layer and the first oxide layer forms a gate dielectric for conductive gate electrodes in the first active area and the second oxide layer forms a gate dielectric for conductive gate electrodes in the second active area. PA1 providing a semiconductor wafer, in which the wafer includes a semiconductor substrate comprising a first region and a second region laterally displaced from the first region; PA1 forming a first dielectric layer on an upper surface of the semiconductor substrate, wherein the first dielectric layer has a first thickness; PA1 depositing a masking layer on the first dielectric layer and patterning the masking layer to expose the first dielectric layer above the second region of the semiconductor substrate; PA1 while retaining a portion of the first dielectric layer above the entirety of the second region, subjecting the wafer to an oxygen bearing ambient at a temperature of 700.degree. C. to 1000.degree. C. such that a second dielectric layer is formed over the second region of the semiconductor substrate, wherein the second layer has a second thickness, and further wherein the second thickness is unequal to the first thickness; PA1 removing the masking from the upper surface of the first dielectric layer, subsequent to the subjecting step; forming first and second gate structures on upper surfaces of the first dielectric layer and the second dielectric layer respectively; and PA1 introducing impurities into a first and second pair of source/drain regions laterally displaced on either side of the first and second channel regions respectively whereby first and second transistors are formed, wherein the dielectric layer serves as a gate dielectric for the transistor and the second dielectric layer serves as a gate dielectric for the second transistor. PA1 stripping a pad oxide and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; PA1 stripping the sacrificial oxide not protected by the photoresist; PA1 stripping the photoresist; and PA1 growing a gate oxide layer which is thinner than the sacrificial oxide layer. PA1 providing a substrate with a device isolation structure thereon; PA1 forming an oxide layer over the substrate and the device isolation structure; PA1 forming a silicon nitride layer over the oxide layer; and PA1 patterning the silicon nitride layer so that portions of the oxide layer are covered by the silicon nitride layer and portions of the oxide layer are exposed, wherein the oxide layer covered by a silicon nitride layer defines an input/output device area, whereas the oxide layer not covered by a silicon nitride layer defines a core device area, PA1 wherein the patterning of the silicon nitride layer further includes: PA1 defining the silicon nitride layer covered input/output device area as a first gate oxide layer; and PA1 defining the silicon nitride layer-free core device area as a second gate oxide layer, and wherein the first gate oxide layer includes a silicon nitride/oxide stack. PA1 forming a first gate dielectric layer over a semiconductor body; PA1 forming a first disposable layer over the first gate dielectric layer, said first disposable layer comprising a material selectively etchable with respect to the first gate dielectric layer and the semiconductor body; PA1 forming a pattern over the first disposable layer, said pattern covering a first region of the disposable layer and exposing a second region of the disposable layer; PA1 removing at least a portion of the first disposable layer in the second region using said pattern; PA1 removing the pattern while the substrate is not exposed; PA1 removing at least a portion of the first gate dielectric layer in the second region; and PA1 subsequent to removing the pattern, forming a second gate dielectric layer in the second region, said second gate dielectric layer having a thickness different from the first dielectric layer. PA1 forming a field oxide region to isolate an active area on a main surface of a semiconductor substrate; PA1 formine a first gate dielectric layer on the active area, PA1 implanting impurities into the substrate through the first gate dielectric layer; PA1 forming a mask on the first gate dielectric layer, the mask having openings over portions of the active area; PA1 etching the first gate dielectric layer to expose the portions of the active area; and PA1 forming a second gate dielectric layer on the exposed portions of the active area to a thickness less than a thickness of the first gate dielectric layer, wherein the first gate dielectric layer is formed to a first thickness in an approximately 20% oxygen atmosphere at about 800.degree. C. to about 1000.degree. C. for about 20 seconds to about 10 minutes and wherein said second gate dielectric layer is formed to a second thickness in an approximately 50% N.sub.2 O atmosphere at about 800 .degree. C. to about 1000.degree. C. for about 2 minutes to about 45 minutes. PA1 implanting dopants through the sacrificial oxide layer; PA1 implanting nitrogen ions without a mask into substrate regions; PA1 subjecting the wafer to a rapid thermal annealing step; PA1 masking the substrate with a photoresist to define locations of the thin oxides of the dual gate oxide; PA1 providing a second implantation of nitrogen through the resist mask; PA1 stripping off the resist mask and sacrificial oxide; and PA1 growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen implanted area.
However, the foregoing integration scheme for providing a dual gate oxide process necessary for use in high performance DRAM systems or logic circuits yields two oxide gates of different thicknesses but without sufficient thickness uniformity and with only thin oxide nitrided.
U.S. Pat. No. 5,960,289 discloses a method for making a dual thickness gate oxide layer using a nitride/oxide composite region. The process entails:
providing a substrate having first and second active areas separated by an isolation region;
The step of forming the protection layer may comprise exposing the semiconductor to an ambient comprising a silicon-containing gas and a nitrogen-containing gas to form the protective layer; and exposing the protection layer to a N.sub.2 anneal ambient.
A process for making a dual gate oxide thickness integrated circuits is disclosed in U.S. Pat. No. 6,033,943. The process comprises:
U.S. Pat. No. 5,863,819 disclose a method for fabricating a DRAM access transistor with dual gate oxide technique. The steps include:
A method for manufacturing a dual gate oxide layer which can be applied to the surface of a shallow trench isolation structure is disclosed in U.S. Pat. No. 5,985,725. The method entails:
U.S. Pat. No. 6,063,670 disclose a method for fabricating an integrated circuit of multiple gate dielectric thicknesses comprising:
A method of manufacturing a semiconductor device of dual gate oxide formation with minimal channel dopant diffusion is disclosed in U.S. Pat. No. 6,030,862. The process comprises:
Accordingly, there is a need in the art of providing dual gate oxide technology for high performance DRAM systems and logic circuits to obtain two oxide thicknesses in one oxidation step through the use of local nitro-en implantation, to provide channel implant anneal for the dual gate process and to improve gate oxide thickness uniformity.